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(ds6110 rev. r) 05/10 pin configuration (top view) 52 pin plastic quad flat pack (pqfp) see page 35 for 64-pin qfn pin configuration 52 - 51 - vddlog 50-rtap 49-rta4 48-rta3 47-rta2 46-rta1 45-rta0 44 - rtmode 43 - bcmode 42 - rcva 41 - txinha 40 - busa str 39 - vdda 38 - 37 - busb 36 - vddb 35 - 34 - txinhb 33 - rcvb 32 - ffempty 31 - rf0 / rcmda 30 - rf1 / rcmdb 29 - 28 - valmess 27 - error busa busb rflag d11-14 d12-15 d13-16 d14-17 d15-18 ra2-19 ra1-20 ra0-21 bcstart - 22 ra3-23 clk-24 gnd-25 mr-26 r/ - 1 -2 d0 - 3 d1 - 4 d2 - 5 d3 - 6 d4 - 7 d5 - 8 d6 - 9 d7-10 d8-11 d9-12 d10-13 w cs hi-6110pqi & hi-6110pqt mil-std-1553 / mil-std-1760 bc / rt / mt message processor hi-6110 may 2010 general description features the hi-6110 is a cmos integrated circuit implementing the mil-std-1553 (1553) data communications protocol between a host processor and a dual redundant 1553 data bus. the single chip architecture has a digital section containing all necessary logic and memory to process and store the command and data words for one complete 1553 message. the analog section includes dual transceivers coupled to the 1553 buses through external current mode transformers. the device is available in an industry standard 64-pin 9 mm square qfn package, making it the smallest dual redundant 1553 interface product on the market. the hi-6110 may be configured as a bus controller (bc), a remote terminal (rt), a monitor terminal (mt), or a monitor terminal with assigned rt address. 16-bit registers store incoming and outgoing command, status and data words. using two 32-word data fifos, the hi-6110 can store the maximum number of 1553 words occurring in any message. for messages with transmitted data words, data may be written in advance or on-the-fly. received data can be retrieved on-the-fly or all at once after the valid message flag is asserted. bc message sequences are initiated by a rising edge on the bcstart input, o ra0to1 transition at the bcstart bit in the control register. all rt command responses are automatically initiated after a valid command word is received. a single encoder services both buses, each of which have a dedicated analog transformer driver. each driver dissipates less than 200 mw of on-chip power at 100% duty cycle. each bus receiver has a dedicated manchester decoder. in bc mode, a rcv signal indicates when valid 1553 words are received. in rt/mt modes, rcv indicates a valid command received, while the 1553 command decoder updates a message register so the external controller can identify command type and respond appropriately. guaranteed by design, the hi-6110 cannot generate messages exceeding 660us, the duration of a command or status word plus 32 contiguous data words. the external host controller reads and writes a simplified register structure in the hi-6110 over a 16-bit parallel bus. the system designer has flexibility over many aspects of configuration. control and status monitoring can be done in hardware (by reading/writing control pins) or in software (by reading/writing register bits). ? monolithic cmos technology ? 3.3v operation ? exceptionally low power ? on-chip message buffering ? selectable master clock frequency ? dual differential 1553 bus transceivers ? bus controller / remote terminal / monitor terminal operating modes ? compliant to mil-std-1553b notice 2 and mil-std-1760 stores management ? ? ? ? ? ? ? applications mil-std-1553 terminals flight control and monitoring eccm interfaces stores management test equipment sensor interfaces instrumentation holt integrated circuits www.holtic.com (
hi-6110 pin descriptions signal function description during i/o operations, data is latched on rising edge. up gnd power supply ground, 0v. master eset, active high. clears all data fifos and all registers except the control, transmit status word and transmit mode data word registers. this i . error out oes high error is resets bcstart is asserted to begin next message. and mt s error resets automatically after 3 to 4us. output signal mirro corresponding status register bit. valmess output goes high at the end of a valid message sequence. signal str input (internal 12k pull- ) r/ input device register access, read = 1, write = 0. (internal 12k pull-up) input chip select for register reads and writes, active low. (internal 12k pull-down) d0 - d15 i/o data bus signals. (internal 12k pull-down per signal) ra0 - ra3 inputs register access address, inputs are ored with corresponding control register bits. (internal 12k pull-down per signal) bcstart input message starts on rising edge when in bc mode. input is ored with a corresponding control register bit, wher ea0to1 transition will also trigger message start. (this input has an internal 12k pull-down.) clk input system clock. (internal 12k pull-down) power mr input r nput is ored with a corresponding control register bit (internal 12k pull-down) put error g when a message detected. in bc mode, error when the for rt mode , this rs a this output mirrors a corresponding status register bit. ffempty output when low, data is available in the receive data fifo for the active bus. this output signal mirrors a corresponding status register bit. output this pin goes low each time the decoder detects a valid 1553 word on the active data bus, set by control register bits 5:4. falling edges occur for command words, status words and mode command data words, but not for data words associated with subaddress commands. signal is not asserted for words on the inactive bus, or for words transmitted by the device itself, e.g., no assertion for command words when in bc mode. use falling edge-triggered logic only; falling edge typically occurs 3us after the detected word's mid-parity. this output mirrors a corresponding status register bit. rf0 / output rf0 function: if ?1? when reading bus a word register, the stored word had data sync. rcmda rcmda function: in rt or mt mode, pin goes high when a valid receive command was decoded on bus a. this output mirrors a corresponding status register bit. rf1 / output rf1 function: if ?1? when reading bus b word register, the stored word had data sync. rcmdb rcmda function: in rt or mt mode, pin goes high when a valid receive command was decoded on bus b. this output mirrors a corresponding status register bit. rcva outputs receive a and receive b flags: in bc mode, these signals go high when any valid rcvb word is received on bus a or bus b. in rt or mt mode, these signals go high when a valid command is received on bus a or bus b. for valid rt-to-rt only, rcv goes high after command word pair. these output signals mirror two corresponding status register bits. txinha input logic one disables the bus a transmitter. (internal 12k pull-up) txinhb input logic one disables the bus b transmitter. (internal 12k pull-up) busa, xfmr positive and negative polarity of 1553 signals for buses a and b. these signal pairs busb, connect the analog transceivers to the external transformer. bcmode input selects operating mode. this input signal is ored with a corresponding control register bit. (internal 12k pull-up) rtmode input selects operating mode. this input signal is ored with a corresponding control register bit. (internal 12k pull-down) rta0-rta4 inputs remote terminal address inputs, for rt mode. (internal 12k pull-up per signal) rtap input this input sets remote terminal address parity, odd. (internal 12k pull-down) vddlog power +3.3vdc 5% power supply input for internal logic vdda, vddb power +3.3vdc 5% power supply inputs for bus a and bus b transceivers w cs rflag busa busb holt integrated circuits 2
hi-6110 signals rf1 and rf0 identify last received 1553 word type signal mode rf1 rf0 bc 00 - - - 0 1 pulses low if valid receive command bus a valid receive command bus a 1 0 - valid receive command bus b valid receive command bus b h reading bus a word or bus b word registers sync type for the stored word can be determined from the rf0 and rf1 outputs. rt or mt with assigned rt address mt without assigned rt address status word 2 w ile the , while the /str input is held low, output rf1 = 1 if the stored bus word had command sync, or output rf0 = 1 if the stored bus word had data sync. table 2. mil-std-1553 word type decoding register read (r/ =1) rt-rt, received status word (from last rt-rt) ra3:0 bc rt or mt with assigned rt address mt without assigned rt address w address mode ra3:0 bc rt or mt with assigned rt address mt without assigned rt address 0000 status word 1 ( if receive rt ) command word 1 command word 1 0001 status word 2 only rt-rt transmit rt command word 2 (from last rt-rt) command word 2 from last rt-rt 0010 - received mode data word bc-transmitted mode data word 0011 - transmit rt status word from last rt-rt 0100 received data fifo received data fifo data fifo, incl. rt-transmitted mode data 0101 status register status register status register 0110 - message register message register 0111 error register error register error register 1000 - - status word (from receiving rt, if rt-rt) 1001 busa word bus a word bus a word 1010 busb word bus b word bus b word 1100 control register control register control register register write (r/ =0) address mode x 0 0 0 command word 1 transmit status word x 0 0 1 command word 2 ( used for rt-rt only) transmit mode data word - x 0 1 0 transmit data fifo reset transmit data fifo - x 0 1 1 - transmit data fifo - x 1 x x control register control register control register w table 1. hi-6110 internal register address map functional description host interface the holt hi-6110 provides a simple interface between a host subsystem and a mil-std-1553 dual redundant data bus. messages are processed one at a time. the hi-6110 automatically handles message formatting, error checking, message data buffering, protocol checking and default responses. the host may override default message responses by updating registers on-the- fly. the host communicates with the hi-6110 using a 16-bit bidirectional data bus. on-chip bus transceivers allow the device to be connected to the mil-std-1553 data buses using external coupling transformers. the hi-6110 can be configured as 1553 bus controller (bc), remote terminal (rt) or bus monitor (mt). the bcmode and rtmode inputs define the mode of operation as follows: bcmode rtmode 1553 operating mode 1 0 bus controller (bc) 0 1 remote terminal (rt) 1 1 bus monitor (no assigned rt address) 0 0 bus monitor with assigned rt address the hi-6110 is further configured by setting various configuration bits in the on-chip control register. different sets of 16-bit registers and message data fifos are available depending upon the mode of operation (bc, rt or mt). the pin is used as the timing signal for data read and write cycles. data is output on the 16-bit bidirectional data bus, d15-d0, when r/ is high and is low. d15-d0 are inputs when r/ is low, and data is written into internal registers on the rising edge of the signal. the chip select input must be low for all register read / write operations: r/ d15-d0 operation 1 x x high impedance no operation 0 x 1 high impedance no operation 0 1 0 output read 0 0 0 input write (on rising edge) four register address inputs (ra3, ra2, ra1, ra0) are used to select internal registers during host read or write operations. note that internal registers may be write-only, read-only or read/write. the register address map is different for bc, rt and mt modes as not all registers are used in each mode. table 1 defines the hi-6110 address map in detail. str w str w str cs cs w str str holt integrated circuits 3
hi-6110 (bus controller mode) valmess error rcva rcvb rf0 rf1 clk mr bcstart bcmode rtmode rflag transceiver transceiver bus a busa busa message status protocol control command word 1 manchester encoder busb busb control register status register bc protocol engine bus b parallel to serial manchester decoder serial to parallel manchester decoder serial to parallel host data interface command word 2 tx data fifo status word 1 status word 2 rx data fifo bc error register d15-d0 r/ ra2-ra0 ffempty cs w str bus a word bus b word txinha txinhb mux figure 1. block diagram - bus controller mode bus controller the hi-6110 is configured for bus controller operation by setting the bcmode input high and the rtmode input low. alternatively, control register bits 3:2 (rtmode:bcmode) may be programmed to 0:1. control register bits 3:2 are logically ored with the input pins with the same signal name. figure 1. shows a block diagram of the hi-6110 in bus controller mode in bus controller mode, the user must first perform a master reset to initialize the bc protocol engine and clear all message registers and data fifos. this may be achieved by pulsing the mr input high, or writing a "1" to control register bit 0. the user must select a master clock (clk) frequency by programming control register bits 11 and 12, and the response time out must be programmed per control register bit 14. refer to the bc register formats section for a full description of available registers and their functions in bus controller mode. initialization holt integrated circuits 4
hi-6110 (bus controller mode) mil-std-1553 message data word 15:0 1514131211109876543210 msb lsb mil-std-1553 message data word 15:0 1514131211109876543210 msb lsb clksel reserved not used repto ra3 ra2 ra1 ra0 trb tra rtmode bcmode bcstart mr msb lsb 1514131211109876543210 1 0 xx x not used 0 the receive data fifo is 32-words deep and holds mil- std-1553 message data. the fifo is cleared by master reset or when bcstart occurs. all mil-std-1553 data words received by the bc are stored in the receive data fifo. a low ffempty flag (output pin or status register bit) means message data is available to be read by the host. successive data reads cause ffempty to go high when the last word is read. receive data fifo (read only) read address: 0100 the transmit data fifo is 32-words deep and holds mil- std-1553 message data. the fifo is cleared on master reset. message data to be transmitted by the bc may be loaded into the transmit data fifo by the host prior to bcstart. any data word must be loaded before mid-parity bit for the 1553 word it follows. words are transmitted in the order they are loaded. transmit data fifo (write only) write address: x010 bit name function 15 - not used in bc mode 14 repto controls the time-out which causes the no response error. 0 17 usec gap (equivalent to 57 usec for 5.2.1.7 of the rt validation test plan) 1 131 usec gap 13 - 12 clksel 10 - 7 ra3:0 register address for hi-6110 register and data read and write operations. the register address is defined by the logical or of these bits and their corresponding input pins. writting control register bits 10:7 to 0000 is necessary if the ra0 - ra3 input pins are used for hi-6110 register addressing. 6- 5 - 4 trb, tra bc d t 3 - 2 rtmode, hi-6110 mode select bits. these control register bits are logically or'ed with their corresponding input pins, bcmode allowing the user to select 1553 operating mode under either hardware or software control: not used in bc mode selects the frequency of the hi-6110 external clk input, as follows: clksel value 0 24 mhz 1 12 mhz 11 reserved this bit must be written to ?0?. not used in bc mode setting either tra or trb to "1" enables transmit on mil-std-1553 bus a or bus b. setting both tra and trb selects neither bus. the protocol engine connects to the selected, active bus. the 1553 receiver, manchester ecoder and rcv output signal are still operational on the inactive bus. valid words received on the inactive bus can be read without changing active bus by reading the bus a word or bus b word register. note: he txinha and txinhb input pins can override bus enablement. rtmode bcmode 1553 operating mode 0 0 bus monitor (mt), with assigned rt address 0 1 bus controller (bc) 1 0 remote terminal (rt) 1 1 bus monitor (mt), without assigned rt address 1 bcstart if initially reset, writing a "1" to this bit initiates a bc message sequence. this bit should be reset before next message. 0 mr master reset. writing "1" and then ?0? to this bit performs the same function as pulsing the mr pin. all register and data fifos are cleared when master reset is asserted. the control register is the exception; it is not affected by master reset. the control register settings determine hi-6110 operating mode, clock frequency and the bus enabled for transmit. it can also be used to address registers for read/write operations, to assert master reset, and to initiate mil-std-1553 message sequences. control register (r/w) write address: x1xx, read address: 1100 register formats (bc mode) holt integrated circuits 5
hi-6110 (bus controller mode) t/r 1514131211109876543210 msb lsb rt address subaddress / mode data word count / mode code t/r 1514131211109876543210 msb lsb rt address subaddress / mode data word count / mode code 1 message error 1514131211109876543210 msb lsb rt address instrumentation service request reserved rrr broadcast command received busy subsystem flag dynamic bus control acceptance terminal flag message error 1514131211109876543210 msb lsb rt address instrumentationr service request reserved rrr broadcast command received busy subsystem flag dynamic bus control acceptance terminal flag 1514131211109876543210 msb lsb bus a/b word 15:0 the command word 1 register is loaded by the host with the mil-std-1553 command word to be issued by the bus controller. bit 10 should be set for transmit, reset for receive. for rt to rt commands, command word 1 register holds the receive command word and command word 2 register holds the transmit command word. used only for rt-to-rt commands, the command word 2 register is loaded by the host with the mil-std-1553 transmit command word addressed to the transmitting remote terminal. the command word 1 register is loaded with the receive command word addressed to the receiving remote terminal. if the next message is not an rt-to-rt transfer, it is necessary to write the transmit/receive bit 10 to ?0?. the status word 1 register holds the returned mil-std-1553 status word received from an rt responding to a bc issued command. for rt to rt commands, the status word 1 register captures the status word returned by the receiving remote terminal, while the status word 2 register captures the status word returned by the transmitting remote terminal used only for rt to rt commands, the status word 2 register captures the mil-std-1553 status word returned by the transmitting remote terminal. command word 1 register (write only) write address: x000 command word 2 register (write only) write address: x001 status word 1 register (read only) read address: 0000 status word 2 register (read only) read address: 0001 bc operation in bc mode, the bus a word register holds the last valid mil- std-1553 word received on bus a. the bus b word register holds the last valid mil-std-1553 word received on bus b. while /strobe is low to read a bus word register, the sync type associated with the stored word can be determined from the rf0 and rf1 pins. the rf1 signal is high for command sync, the rf0 signal is high for data sync. bus (read only) read address: 1001 bus b word register (read only) read address: 1010 a word register holt integrated circuits 6
hi-6110 (bus controller mode) 1514131211109876543210 msb lsb not used rcvb rcva not used rflagn ffempty error valmess idle not used 0000000 00 sw1err sw2err manerr norcv 1514131211109876543210 msb lsb not used 00000 fferr not used conerr csycerr dsycerr 0 proerr not used 0 bit name function 15 - 11 - not used. these bits are set to "0". 10 proerr protocol error: extraneous word detected on the bus during a message sequence. 9 sw1err status word 1 error: in an rt-rt sequence. the receiving rt status word has the wrong rt address. for rt to rt transfers, sw1err reports an error in the status word received from the receiving rt. 8 sw2err status word 2 error: 7 fferr data fifo error: data was not available in the transmit data fifo in time to allow transmission. 6 - not used. 5 conerr contiguous message error: transmission was not contiguous. 4- 3 csycerr command sync error: expected command sync, but got data sync. 2 dsycerr data sync error: expected data sync, but got command sync. 1 manerr manchester encoding error: the decoder detected an error in manchester encoding, bit count or parity. 0 norcv this bit is set when a data word is expected while processing a receive command, but a gap is detected. it is also set when an rt-to-rt "no response timeout" occurs, as defined per mil-hdbk-1553, figure 8 "rt-rt timeout measurement". the hi-6110 asserts this error when the bus dead-time between the rt- rt command pair and the transmit rt status word exceeds 15 us when control register bit 14 = "0" or 129us when control register bit 14 = "1". in an rt-rt sequence. the transmitting rt status word has the wrong rt address. this bit is set to "0". not used. this bit is set to "0". the bc error register is cleared at reset and at the beginning of each mil-std-1553 message sequence. if an error is encountered during message execution, the error pin goes high, the error bit is set in the status register, and one or more bits are set in the error register. after the error condition is flagged, the error register should be interrogated before the receipt of the next manchester word. error register (read only) read address: 0111 bit name function 15- 9 - not used. these bits are set to "0". 8 error this bit is "0" after master reset or if the last mil-std-1553 message sequence was valid. error is set to a "1" if the last sequence had an error. the nature of the message error can be determined by examining the error register. the error output pin reflects the state of this bit. 7 valmess this bit is a "0" after reset or the last mil-std-1553 message containing an error. valmess goes high on the completion of an error-free mil-std-1553 message sequence. valmess is reset to a zero at the start of each new bc message. the valmess output pin reflects the state of this bit. 5-6 - not used. 4 rflagn this bit goes low any time a status word is received 3 ffempty if "0" then the receive data fifo contains at least one word of data. this bit is set to a "1" on reset, or when a new bc command sequence is initiated, or when the user has read all available received data words from the receiver data fifo. the ffempty output pin reflects the state of this bit. 2 rcvb set to a "1" if the bus b word register holds a valid mil-std-1553 word. 1 rcva set to a "1" if the bus a word register holds a valid mil-std-1553 word. 0 idle if "1" then the bus controller is idle. this bit is a zero throughout the time a mil-std-1553 message is in progress. the bit returns to a "1" when the message is completed. the status register may be interrogated by the host at any time. it provides information that allows the user to determine whether the hi-6110 is busy executing a mil-std-1553 message and its progress. after a message sequence has completed, the status register indicates whether an error was detected or if the message sequence was successful. status register (read only) read address: 0101 bc operation holt integrated circuits 7
hi-6110 (bus controller mode) issuing bc commands register operations in the hi-6110 can be addressed using either the ra0-ra3 inputs or the ra3:ra0 bits in the control register. each ra input is logically ored with its corresponding control register bit. when using input pins for register addressing, the control register bits 10:7 must be reset. register addressing via control register bits 10:7 is a 2-step process. first, the target register address is written to the control register (and the ra0-ra3 inputs must be held low). next, the desired register operation is performed: the control register provides the register address while the r/ and inputs specify data direction and clock the data transfer. a mil-std-1553 bus controller message can be pre- loaded into the hi-6110 by writing the required command word to the command word 1 register. the command word 2 register is used to hold the second (transmit) command word for rt to rt commands. message data for mil-std-1553 receive commands are loaded by the host into the transmit data fifo. for mode code commands with data word, a data word to be transmitted must be written to the transmit data fifo. a bc message sequence commences when a positive edge occurs at the bcstart input pin, or when control register bit 1 (bcstart) transitions from 0 to 1 as a result of a register write operation by the host. control register bit 1 is not automatically reset upon bc message sequence execution. therefore, when using the control register to start message sequences, it is first necessary to reset bit 1 before it is set to initiate the next message sequence. the mil-std-1553 message is properly formatted by the hi- 6110 and output on the selected mil-std-1553 data bus. the hi-6110 waits for a response from the mil-std-1553 bus if the command type expects a response. the responding rt's status word is captured in the hi-6110 status word 1 register. the status word 2 register is used to capture the status word from the transmitting rt during rt-to-rt transfer commands. message data words received from the transmitting rt are stored in the receive data fifo. a mode data word received from the transmitting rt is also stored in the receive data fifo. if the reply from the mil-std-1553 responding terminal was a valid response and met all response time, sync and data encoding, parity checks, word count, rt address, and contiguous message requirements, then the valmess output pin goes high and bit 7 in the status register is set. the host may then retrieve the contents of the status word register(s) and receive data fifo as required by the application software. the ffempty output pin will be low if the fifo contains at least one data word, and the corresponding bit 3 in the status register will be reset. when all data words have been read by the host controller, the ffempty output pin goes high, and bit 3 in the status register is set. the final result of any bc message sequence is assertion of either a valmess flag or an error flag. if an error is detected during a mil-std-1553 message sequence, the error output pin is asserted, corresponding bit 8 in the status register is set, and the appropriate error bit(s) are set in the error register. the host may interrogate the error register to determine what action is necessary to correct the error. the valmess output remains low for any message for which an error is detected. there are limited circumstances when valmess may be followed by error. for example, if the bc requests an rt response with 4 data words but instead receives 5, the extra data word will cause the valmess flag to be reset and error to be set. the host controller has the option of reading rt responses on-the-fly by monitoring the and ffempty flags, or may simply wait for end of sequence flags, valmess or error. while the transmit data fifo may be pre-loaded before starting a message sequence, any data word may be loaded on the fly, as long as it is written before mid-sync during that word?s transmit window. in order to have the full 32 word capacity available, the transmit data fifo should be cleared before writing data. the fifo is cleared at master reset, or when valmess or error is asserted at the end of a message. the receive data fifo is cleared at master reset, or by performing a series of fifo read operations until ffempty goes high. the receive data fifo will not accept new receive data when full. the fifo must have at least one empty register by mid-sync within the time window for any incoming data word. w stb rflag holt integrated circuits 8
hi-6110 (bus controller mode) receive command data word 1 data word 2 status word (tx) from hi-6110 bus controller from transmitting rt mil-std-1553 bus bcstart valmess str host write cw1 (receive command) host read sw1 (status word rx) host write cw2 (transmit command) transmit command host read data fifo (data word 1) host read data fifo (data word 2) host read sw2 (status word tx) status word (rx) from receiving rt ffempty transmit command data word 1 data word 2 status word from hi-6110 bc from rt mil-std-1553 bus bcstart valmess str host write cw1 (command word) host read data fifo (data word 1) host read data fifo (data word 2) host read sw1 (status word) ffempty receive command data word 1 data word 2 data word 3 status word from hi-6110 bus controller from rt mil-std-1553 bus bcstart valmess str host write cw1 (command word) host write data fifo (data word 1) host write data fifo (data word 2) host write data fifo (data word 3) host read sw1 (status word) the hi-6110 bus controller issues an rt to rt transfer with 2 data words to two remote terminal on the bus. the rts execute the command and the bus controller validates the rt responses. note that the data transferred is captured by the hi-6110 bus controller and may be read by the host. example 3. rt to rt transfer (rtrt message) the hi-6110 bus controller issues a transmit command requiring a 2 data word response to a remote terminal on the bus. the correct status word and 2 data words are received and read by the host. example 2. rt to bc transfer (rtbc message) the hi-6110 bus controller issues a receive command with 3 data words to a remote terminal on the bus. the correct status word is received. example 1. bc to rt transfer (bcrt message) example bc mil-std-1553 message sequences holt integrated circuits 9
hi-6110 (bus controller mode) mode code command mode data status word from hi-6110 bc from rt mil-std-1553 bus bcstart valmess str host write cw1 (command word) host write data fifo (mode data) host read sw1 (status word) mode code command mode data status word from hi-6110 bc from rt mil-std-1553 bus bcstart valmess str host write cw1 (command word) host read data fifo (mode data) host read sw1 (status word) ffempty mode code command status word from hi-6110 bus controller from rt mil-std-1553 bus bcstart valmess str host write cw1 (command word) host read sw1 (status word) the hi-6110 bus controller issues a mode command with data word (receive) to a remote terminal on the bus. the correct status word is returned and read by the host. example 6. mode code with data word (receive) the hi-6110 bus controller issues a mode command with data word (transmit) to a remote terminal. the status word and mode data word are received; the data word is stored in the receive fifo. status word and mode data are read by the host. example 5. mode code with data word (transmit) the hi-6110 bus controller issues a mode code command to a remote terminal on the bus. the correct status word is received. example 4. mode code command without data word example bc mil-std-1553 message sequences holt integrated circuits 10
hi-6110 (bus controller mode) mode code command from hi-6110 bc mil-std-1553 bus bcstart valmess str host write cw1 (command word) host write data fifo (mode data) mode data mode code command from hi-6110 bc mil-std-1553 bus bcstart valmess str host write cw1 (command word) receive command data word 1 data word 2 status word (tx) from hi-6110 bus controller from transmitting rt mil-std-1553 bus bcstart valmess str host write cw1 (receive command) host read sw2 (status word tx) host write cw2 (transmit command) transmit command host read data fifo (data word 1) host read data fifo (data word 2) receive command data word 1 data word 2 data word 3 from hi-6110 bus controller mil-std-1553 bus bcstart str host write cw1 (command word) host write data fifo (data word 1) host write data fifo (data word 2) host write data fifo (data word 3) valmess the hi-6110 bus controller issues a broadcast mode command with data word to all remote terminals on the bus. example 10. broadcast mode code with data word the hi-6110 bus controller issues a broadcast mode command without data word to all remote terminals on the bus. example 9. broadcast mode code without data word the hi-6110 bus controller issues a broadcast rt to rt transfer command with 2 data words to a remote terminal on the bus. the rt broadcasts the message and the bus controller validates the rt response. the transmitted data words are captured by the hi-6110 bus controller and may be read by the host controller. example 8. broadcast rt to rt(s) transfer the hi-6110 bus controller issues a broadcast receive command with 3 data words to all remote terminals. example 7. broadcast bc to rt(s) transfer example bc mil-std-1553 message sequences holt integrated circuits 11
hi-6110 (remote terminal mode) figure 2. block diagram - remote terminal mode valmess error rcva rcvb rcvcmda rcvcmdb clk mr bcstart bcmode rtmode rta4-rta0 rtap rflag transceiver transceiver bus a busa busa message status protocol control terminal address status word manchester encoder busb busb control register status register rt protocol engine bus b parallel to serial manchester decoder serial to parallel manchester decoder serial to parallel host data interface tx data fifo command word 1 command word 2 rx data fifo rt error register message register d15-d0 r/ ra3-ra0 ffempty cs w str bus a word bus b word txinha txinhb mode data (r) mode data (w) status word rec'd remote terminal the hi-6110 is configured for remote terminal operation by setting the bcmode input low and the rtmode input high. an alternative is programming control register bit 2 (bcmode) to a "0" and programming control register bit 3 (rtmode) to a "1". these control register bits are logically ored with their corresponding input pins. figure 2. shows a block diagram of the hi-6110 in remote terminal mode. in remote terminal mode, the host controller first performs a master reset to initialize the rt protocol engine and clear all message registers and data fifos. this may be achieved by pulsing the mr input high, or writing a "1" and then a ?0? to control register bit 0. the user must select a master clock (clk) frequency by programming control register bits 11 and 12. refer to the rt register formats section for a full description of available registers and their functions in remote terminal mode. initialization holt integrated circuits 12
hi-6110 (remote terminal mode) 1514131211109876543210 msb lsb bus a/b word 15:0 mil-std-1553 message data word 15:0 1514131211109876543210 msb lsb clksel reserved idwt repto ra3 ra2 ra1 ra0 trb tra rtmode bcmode not used mr msb lsb 1514131211109876543210 0 1 not used ra0 rerr x x 0 in rt mode, the bus a word register holds the last valid mil-std-1553 word received on bus a. the bus b word register holds the last valid mil-std-1553 word received on bus b. bus (read only) read address: 1001 bus b word register (read only) read address: 1010 a word register the 32-word transmit data fifo holds mil-std-1553 message data. the fifo is cleared by master reset, at assertion of valmess or error outputs, or by any write to register address x010. see section, ?ac electrical characteristics? for special timing requirements when writing to register address x010 to reset the fifo. each data word for transmit must be written into the fifo before mid-parity bit transmission for the preceding mil-std-1553 word occurs. words are transmitted in the order loaded. r fifo eset transmit data write address: x010 transmit data fifo (write only) write address: x011 bit name function 15 - not used. 14 repto controls the time-out which causes the no response error. 0 17 usec gap (equivalent to the 57 usec measurement of 5.2.1.7 of the rt validation test plan) 1 131 usec gap 13 idwt inhibit data word transmission. when ?illegal command detection? is required, this feature alows ?command illegalization?. when the idwt bit is set, normal transmission of ordinary and mode data words is suppressed for all transmit commands. note: there will be no valmess or error assertion for the affected message. for normal response to the next command, this bit must be reset before that command?s status word bit 0 is transmitted. 12 clksel selects the frequency of the hi-6110 external clock input. clksel equals ?0? selects a 24 mhz clock while clksel equals ?1? selects a 12 mhz clock. 11 reserved this bit must be reset to ?0? 10 - 7 ra3:0 register address for hi-6110 register and data read / write operations. the register address is defined by the logical or of these bits and their corresponding input pins. setting control register bits 10:7 to 0000 ensures that only the input pins are used for addressing registers. 6 rerr reset error. if rerr is low, the error output pin can only be reset by asserting mr, master reset. writing rerr high causes the error output to be reset (rising edge). if the rerr is left high, the error output will automatically reset after 3 to 4 microseconds. for normal operation, this bit is set to ?1?. 5 - 4 trb, tra setting either tra or trb to "1" enables transmission on mil-std-1553 bus a or bus b. setting both tra and trb selects neither bus. the rt protocol engine connects to the selected, active bus. the 1553 receiver, manchester decoder and rcv output signal are still operational on the inactive bus. this is useful when the remote terminal receives a command on the inactive bus, indicated by rcv signal output. the rt must switch active buses to service the command. valid words received on the inactive bus can be read without changing active bus by reading the bus a word or bus b word register, but the terminal cannot respond as transmit is disabled. note: the txinha and txinhb input pins can override bus enablement. 3 - 2 rtmode, hi-6110 mode select. these control register bits are logically or'ed with their corresponding input pins, bcmode allowing the user to select 1553 operating mode under either hardware or software control: rtmode bcmode 1553 operating mode 0 0 bus monitor (mt), with assigned rt address 0 1 bus controller (bc) 1 0 remote terminal (rt) 1 1 bus monitor (mt), without assigned rt address 1 - not used in rt mode. 0 mr master reset. writing "1" and then ?0? to this bit performs the same function as pulsing the mr pin. all registers and data fifos are cleared when master reset is asserted. the control register is the exception; it is not affected by master reset. the control register value specifies hi-6110 operating mode, clock frequency and the bus enabled for transmit. it can also be used to address registers for read/write operations, assert master reset, as well as data word suppression when illegal command detection is implemented . control register (r/w) write address: x1xx, read address: 1100 register formats (rt mode) holt integrated circuits 13
hi-6110 (remote terminal mode) message error 1514131211109876543210 msb lsb rt address instrumentation service request reserved rrr broadcast command received busy subsystem flag dynamic bus control acceptance terminal flag message error 1514131211109876543210 msb lsb rt address instrumentation service request reserved, must be ?000? rrr broadcast command received busy subsystem flag dynamic bus control acceptance terminal flag t/r 1514131211109876543210 msb lsb rt address subaddress / mode data word count / mode code 1 t/r 1514131211109876543210 msb lsb rt address subaddress / mode data word count / mode code mil-std-1553 message data word 15:0 1514131211109876543210 msb lsb updated only during rt to rt transmit messages, the received status word register captures the mil-std-1553 status word transmitted by the receiving remote terminal. received address: 0011 status word register (read only) read the transmit status word register holds bits 10:0 for the status word transmitted by the remote terminal in response to a (non-broadcast) command. status word bits 15:11 are automatically set to match the rt address present at the rta4:0 input pins. the hi-6110 automatically transmits a status word in response to valid non-broadcast commands. the register may be changed anytime prior to status word mid-sync bit. the transmit status word register is not affected by mr, master reset, and bits 10:0 must be set to?0? at terminal initialization. transmit word address: x000 status register (write only) write if the last valid command received was rt to rt, the command word 2 register contains the second (transmit) command word. (see note above for command word 1.) whenever message register bit 3 or bit 9 is set, the valid command is contained in the command word 2 register. whenever rcv is asserted, the active command word register can always be determined by checking message register bits 3 and 9. command word 2 register (read only) read address: 0001 for all commands except rt to rt, the command word 1 register contains the last valid command word received. if the last valid command received was rt to rt, the command word 1 register holds the first (receive) command word and the command word 2 register holds the second (transmit) command word. then if message register bits 3 and 9 are both 0, the command word 1 register contains the valid command. command word 1 register (read only) read address: 0000 the receive data fifo is 32-words deep and holds mil- std-1553 data words received by the rt. the fifo is cleared on master reset or after all words have been read by the host. a low ffempty flag (pin or status register) means fifo data is available to be read by the host. successive data reads cause ffempty to go high when the last data word is read. receive data fifo (read only) read address: 0100 rt operation holt integrated circuits 14
hi-6110 (remote terminal mode) rtparerr manerr norcv 1514131211109876543210 msb lsb not used 00000 fferr not used conerr gaperr seqerr syncerr 0 not used 0 not used 0 1514131211109876543210 msb lsb rf1 rcvb rcva rf0 rflagn ffempty error valmess idle not used 0000000 bit name function 15 - 10 - not used. these bits are set to "0". 9 rtparerr rt parity error in the pin-programmed rt address. rt address parity is checked only at master reset, and once this bit is set, the host controller must perform a subsequent master reset to update parity status. 8 7 fferr data was not available in the transmit data fifo. 6 - not used. 5 conerr contiguous message error: transmission was not contiguous. 4 gaperr 3 seqerr the next event after a command word was erroneous. for example, a gap following a valid receive command word, or a contiguous data word following a transmit command word. 2 syncerr sync error: expected command sync and got data sync, or vice versa. 1 manerr manchester encoding error: the decoder detected an error in manchester encoding, bit count or parity. 0 norcv - not used. this bit is set to "0". this bit is set to "0". bus activity was detected in the 4.0 us gap after a valid message was completed. this bit is set when a data word is expected while processing a receive command, but a gap is detected. it is also set when an rt-to-rt "no response timeout" occurs, as defined per mil-hdbk-1553, figure 8 "rt-rt timeout measurement". the hi-6110 asserts this error when the bus dead-time between the rt- rt command pair and the transmit rt status word exceeds 15 us. the rt error register is cleared at master reset and error flags are automatically reset if control register bit 6 = ?1?. if an error is encountered during message execution, the error pin goes high, the error bit is set in the status register, and one or more bits are set in the error register to specify the type of error detected. error register (read only) read address: 0111 bit name function 15- 9 - not used. these bits are set to "0". 8 error this bit is reset to "0" after mr, and will automatically reset 2 to 3 us after assertion if control register rerr bit is set. error is set to a "1" if the last sequence had an error. the nature of the message error can be determined by examining the error register. the error output pin reflects the state of this bit. 7 valmess this bit is a "0" after reset or after a mil-std-1553 message containing an error. valmess goes high upon completion of an error-free mil-std-1553 message sequence. valmess is reset to a zero each time a valid command is received on the active bus. the valmess output pin mirrors the state of this bit. 6 rf1 this bit goes high when a valid receive command arrives on bus b. it is reset by the rcv b flag. 5 rf0 this bit goes high when a valid receive command arrives on bus a. it is reset by the rcv a flag. 4 rflagn during a message sequence this bit goes low at the arrival of a command word, status word, or mode data word. for consecutive words, this bit will momentarily go high between words. the output reflects the state of this bit. 3 ffempty if "0", the receive data fifo contains at least one unread data word. this bit is set to "1" upon master reset, or when the user has read all available received data words from the receiver data fifo. the ffempty output pin reflects the state of this bit. 2 rcvb set to "1" upon receipt of a valid command word on bus b except for rt-to-rt receive commands when it is set after the second command word is received. the rcvb output pin mirrors the state of this bit. 1 rcva set to "1" upon receipt of a valid command word on bus a .a 0 idle if "1", the rt is idle. this bit is ?0? throughout the time the rt is processing a valid mil-std-1553 command message. the bit returns to a "1" when the message is completed. rflag except for rt-tort receive commands when it is set after the second command word is received the rcv output pin mirrors the state of this bit. the status register may be interrogated by the host at any time. it provides information that allows the user to determine whether the hi-6110 is busy executing a mil-std-1553 message and its progress. after a message sequence has completed, the status register indicates whether an error was detected or if the message sequence was successful. status register (read only) read address: 0101 rt operation holt integrated circuits 15
hi-6110 (remote terminal mode) don't care x msb lsb xxxxxxxxxxxxxxx msb lsb 1514131211109876543210 0 0 13 12 not used 11 10 98765432 0 1 message type flags mode data word 15:0 1514131211109876543210 msb lsb mode data word 15:0 1514131211109876543210 msb lsb performing a host write cycle to register address x010 causes the transmit data fifo to be cleared. new data may be loaded into the fifo by writing to register address x011 as described above. note that no data is stored when performing a write cycle to register address x010 and the actual data presented on the databus is not used (don't care). reset transmit data fifo (write only) write address: x010 15:11 10 9:5 4:0 15:11 10 9:5 4:0 rta 0 xxxxx 11111 0 00001 - 11110 00001 - 11110 xxxxx rta 0 00001 - 11110 xxxxx xxxxx 1 00001-11110 xxxxx 11111 0 00001 - 11110 xxxxx not rta 1 00001-11110 xxxxx rta 1 00001 - 11110 xxxxx not 11111 0 00001 - 11110 xxxxx rta 1 00001-11110 xxxxx 11111 0 00001 - 11110 xxxxx rta 1 00001-11110 xxxxx rta 1 0000 or 11111 0xxxx command word 2 11111 1 0000 or 11111 0xxxx only applies for rta 0 0000 or 11111 0xxxx rt-rt commands 11111 0 0000 or 11111 0xxxx rta 1 0000 or 11111 1xxxx 11111 1 0000 or 11111 1xxxx rta 0 0000 or 11111 1xxxx 11111 0 0000 or 11111 1xxxx non-mode commands 0001 receive command from bc, not broadcast 0080 0004 0100 0402 transmit command, rt 0410 o m 0400 * receive command from bc, broadcast receive command, rt-rt, not broadcast receive command, rt-rt, broadcast to bc 1008 transmit command, rt-rt, not broadcast 0200 transmit command, rt-rt, broadcast mc0 - mc15 t/r=1 n ode data, not broadcast mc0 - mc15 t/r=1 no mode data, broadcast 0410 mc0 - mc15 t/r=0 not broadcast, undefined 0400 mc0 - mc15 t/r=0 broadcast, undefined 2420 mc16 - mc31 t/r=1 mode data, not broadcast 0400 * mc16 - mc31 t/r=1 broadcast, undefined 0040 mc16 - mc31 t/r=0 mode data, not broadcast 0800 mc16 - mc31 t/r=0 mode data, broadcast * two cases where 0400 is reset 550ns after rcv mode code commands command word 1 bit fields command word 2 bit fields hex last valid command decoded the message register identifies command type when a new valid command is received from the mil-std-1553 bus controller. when a valid command is received, message type is decoded and appropriate message register bit(s) are set. two bit pairs are mirrored: bit pair 3 and 12, bit pair 5 and 13. in the table below, ?rta? indicates assigned remote terminal address. broadcast command occurs when address = 11111. bit 10 is set for mode code or non-rt-rt transmit commands where bits 15:11 equal rta or 11111. bit 10 enables detection and ?illegalization? for three undefined mode code command types listed in the table below. message register (read only) read address: 0110 the read-only receive mode data egister holds the value of ode ata ord received during a ode ode with ata ord ( eceive) ommand addressed to this rt. word r the last m d w m c d w r c this register is reset only by mr master reset. receive mode data word register (read only) read address: 0010 the write-only transmit mode data egister is loaded by the host with the mode data word transmitted by the in response to a ode ode with ata ord ( ransmit) ommand. mode data word r to be remote terminal m c mode d w t c the transmit word register is not affected by mr, master reset. transmit mode data word register (write only) write address: x001 rt operation holt integrated circuits 16
hi-6110 (remote terminal mode) remote terminal operation the hi-6110 remote terminal (rt) address is set by wiring the rta4:rta0 input pins to the desired address. rta0 is the least significant address input. the rtap input must be set/reset to reflect odd parity for the ra4:0 address inputs. upon master reset, the hi-6110 reads the rt address inputs and checks for correct parity. if a parity error is detected, the parerr bit is set in the error register and the hi-6110 rt will not respond to mil-std-1553 command words. the host controller must correct the rt address- parity mismatch, then reassert master reset to enable bus operations. when configured as a remote terminal, the hi-6110 continuously monitors both mil-std-1553 buses. each received command word is checked for validity. the rcva and rcvb outputs are asserted only when a received command is valid. valid is defined as having an rt address matching the pin-programmed rt address or the command is a broadcast command. if a valid command is received on bus a, the rcva signal goes high to notify the host. similarly, when a valid command arrives on bus b, the rcvb signal goes high. the received command may be read from the appropriate command word register, or the message register may be read to quickly determine the type of response needed. the rt protocol sequencer will initiate a response in accordance with the requirements of mil-std-1553. if the message type requires a status word response and the bus tr bit is set in the control register, the hi-6110 rt will automatically transmit its status word approximately 7 to 9 us after rcva or rcvb goes high. the status word register can be modified up to 1.3 us past mid-sync, occurring when the status word is transmitted. if transmit data words are part of the command response, the automatic response delay provides time for the host to load the transmit data fifo. the first data word must be written to the fifo not later than 20 us after status word mid-sync. all data words must be written before mid-sync occurring within its transmission window. all data words may be written in rapid succession once rcva or rcvb goes high. upon error-free completion of the message, valmess goes high. (one exception: broadcast mode code commands without mode data word do not generate valmess.) if an error is detected, valmess remains low and the error signal goes high. the error register can be read to determine error type. in applications requiring illegal command detection, the hi-6110 readily handles command ?illegalization?. upon detecting an illegal command, the host microcontroller takes steps to (a) send the remote terminal status word with the message error (me) bit set (non-broadcast commands only), and (b) suppress transmission of any data words associated with the normal response to the command. for part (a), the status word register is modified by setting the me bit. this is done first to make sure the change is effective before status word transmission begins. for part (b), bit 13 in the control register is set to suppress data word transmission. note: once bit 13 is set in the control register, the affected message will not conclude with valmess or error assertion. control register bit 13 should be written to a zero before the next message is processed. the host might perform the control register write as part of the rcv flag service routine in order to restore normal operation for legal commands. the receive data fifo is cleared at master reset, or by performing a series of fifo read operations until ffempty goes high. the receive data fifo will not accept new receive data when full. when the control register is written to change the active bus, the hi-6110 automatically resets any message in process on the former bus and begins a new message sequence on the new bus. to comply with rt response time limits, it is typically necessary to write the control register within 2 us of the rising edge of the rcv flag on the alternate bus. note that when the active bus is switched, the rt message sequencer retrieves and responds to the last valid command word received on the previously inactive bus. this applies regardless of when the command word was received. for this reason, bus switching should only occur in response to a current rcv or rcmd signal or otherwise be followed by a master reset. the hi-6110 readily handles superseding commands. for superseding commands on the same bus as described in 5.2.1.4 of the rt validation test, the 6110 will generate a new rcv flag upon receiving a valid command after a 4 us gap. the message sequencer is automatically reset and the new sequence initiated. rt validation section 5.2.1.8 ?bus switching? tests a condition otherwise prohibited by the 1553 standard: overlapping valid commands on the two buses. to meet the requirements of this test, certain steps are required: (a) when switching buses for the superseding command, reset control register tra and trb bits for 200 ns minimum before setting the trx bit for the newly active bus. this resets transmission for an in-process command response. to simplify the software, the example software does this for all bus switching. (b) the rt should always respond to the command occurring last. a potential problem occurs when an rt- rt receive command is interrupted by a valid command on the other bus. although cw1 is valid for the remote terminal, rcv for all rt-rt commands occurs after cw1 and cw2 are both received. when a valid command that overlaps cw1 occurs on the other bus, its rcv will go high before the rt-rt rcv. the overlapping command occurs later, although its rcv precedes the rt-rt rcv. the rt-rt rcv must be ignored. to correctly respond to the overlapping command, the software must utilize the rcmda and rcmdb signals as described below. please refer to the software example in the reference design for a working implementation. the rcmda output goes high when a valid non-mode receive command is decoded on bus a. the rcmdb signal performs the same function for bus b. successful compliance with rt validation 5.2.1.8 ?bus switching? requires host interaction when rcmd is asserted for the inactive bus. when this occurs, the host should immediately make that bus active. if an ordinary receive command is coming from the bus controller, rcv for the newly-active bus will go high about 4 us after rcmd. if an rt-rt receive command, rcv follows rcmd by 20 us. in either case once rcv is asserted, the rt can begin polling ffempty to acquire received data words as they arrive. holt integrated circuits 17
hi-6110 (remote terminal mode) receive command data word 1 data word 2 status word 1 from mil-std-1553 bus from hi-6110 rt mil-std-1553 bus str host read and decode message register host read swr (status word received) host read cw2 (transmit command) transmit command host write sw (status word), optional host write data fifo (data word 1) status word 2 from receiving rt valmess ffempty host write data fifo (data word 2) rcva/b transmit command data word 1 data word 2 status word from mil-std-1553 bus from hi-6110 rt mil-std-1553 bus str host write sw (status word), optional host write data fifo (data word 1) host write data fifo (data word 2) host read cw1 (command word) valmess rcva/b ffempty host read and decode message register receive command data word 1 data word 2 data word 3 status word from mil-std-1553 bus from hi-6110 rt mil-std-1553 bus valmess str host write sw (status word), optional host read data fifo (data word 1) host change bus if required rcva/b ffempty host read data fifo (data word 2) host read data fifo (data word 3) host read and decode message rcmda/b the hi-6110 rt receives an rt to rt transfer with 2 data words command from the mil-std-1553 bus. in this case, the hi-6110 is the transmitting rt. the hi-6110 issues the necessary status word and data words, and monitors the acknowledging status word from the receiving rt. example 3. rt to rt transfer, hi-6110 is the transmitting rt the hi-6110 rt receives a transmit command with 2 data words from the mil-std-1553 bus. the host controller hi-6110 rt reads the command word to determine number of data words, and updates the status word register and the requested number of data words. example 2. rt to bc transfer the hi-6110 rt receives a receive command with 3 data words from the mil-std-1553 bus. the hi-6110 captures the message data words and outputs a status word. example 1. bc to rt transfer example rt mil-std-1553 message sequences holt integrated circuits 18
hi-6110 (remote terminal mode) mode code command mode data status word from mil-std-1553 bus from hi-6110 rt mil-std-1553 bus str valmess rcva/b ffempty host write sw (status word) host read cw1 (control word) host write mode (mode data) host read and decode message register mode code command status word from mil-std-1553 bus from hi-6110 rt mil-std-1553 bus valmess str host read cw1 (command word) host write sw (status word) rcva/b ffempty host read and decode message register receive command data word 1 data word 2 status word 1 from mil-std-1553 bus from transmitting rt mil-std-1553 bus str host change bus if required host read and decode message transmit command status word 2 from hi-6110 rt valmess rcva/b ffempty host read data fifo (data word 1) host read data fifo (data word 2) rcmda/b the hi-6110 rt receives a mode command with data word (transmit) from the mil-std-1553 bus. the required status word and mode data word are transmitted by the hi-6110 rt. in this particular example, the host updates both the status word and mode data registers prior to rt response. a update must be completed within if no host writes are performed, the hi-6110 will output the current values of the sw register and mode data register. status word 5us after the rcva/b rising edge. example 6. mode code with data word (transmit) the hi-6110 rt receives a mode code command without data word from the mil-std-1553 bus. the correct status word is output. the is , in this example, the host updates the status word register prior to rt response. status word update must be completed within 5us after the rcva/b rising edge. if no host write performed the hi-6110 will output the current value of the sw register. example 5. mode code command without data word the hi-6110 rt receives an rt to rt transfer with 2 data words command from the mil-std-1553 bus. in this case, the hi-6110 is the receiving rt. the hi-6110 captures the message data and issues the necessary status word. in this particular example, the host did not update the status word register and the hi-6110 re- issues the last value of sw. example 4. rt to rt transfer, hi-6110 is the receiving rt example rt mil-std-1553 message sequences holt integrated circuits 19
hi-6110 (remote terminal mode) receive command data word 1 data word 2 status word 1 from mil-std-1553 bus from hi-6110 rt mil-std-1553 bus str host read and decode message register host write data fifo (data word 2) host read cw2 (transmit command) transmit command host write sw (status word) valmess ffempty rcva/b host write data fifo (data word 1) mil-std-1553 bus receive command data word 1 data word 2 data word 3 str host read and decode message host read data fifo (data word 1) ffempty host read data fifo (data word 2) host read data fifo (data word 3) host change bus if required valmess rcva/b rcmda/b mode code command mode data status word from mil-std-1553 bus from hi-6110 rt mil-std-1553 bus str host read and decode message register host read mode (receive mode data) valmess rcva/b ffempty the hi-6110 rt receives a broadcast rt to rt transfer command with 2 data words from the mil-std-1553 bus. the hi-6110 rt is the transmitter. note that rcva/b doesn?t go high until the transmit command matching the hi-6110 rt address is received. the hi-6110 broadcasts the message and does not wait for a status word to be returned. example 9. broadcast rt to rt transfer hi-6110 is the transmitting rt the hi-6110 rt receives a broadcast receive command with 3 data words from the mil-std-1553 bus. no status word is returned. example 8. broadcast bc to rt transfer the hi-6110 rt receives a mode command with data word (receive) from the mil-std-1553 bus. the correct status word is returned and the host reads the mode data value. in this particular example, the host reads the message register to determine what type of mil-std-1553 command was received. a default value is used for the status word response. example 7. mode code with data word (receive) example rt mil-std-1553 message sequences holt integrated circuits 20
hi-6110 (remote terminal mode) mode code command from hi-6110 bc mil-std-1553 bus valmess str host read cw1 (command word) host read mode (mode data) mode data ffempty rcva/b mode code command from mil-std-1553 bus mil-std-1553 bus valmess str host read cw1 (command word) ffempty rcva/b receive command data word 1 data word 2 status word 1 from mil-std-1553 bus from transmitting rt mil-std-1553 bus str host change bus if required host read and decode message transmit command ffempty host read data fifo (data word 1) host read data fifo (data word 2) valmess rcva/b rcmda/b the hi-6110 rt receives a broadcast mode command with data word from the mil-std-1553 bus. the host reads the mode data word received. example 12. broadcast mode code with data word the hi-6110 rt receives a broadcast mode command without data word from the mil-std-1553 bus. the mode command word is read by the host. note:the rcv signal pulse is less than 1 us wide, and message register flag is cleared at the same time. example 11. broadcast mode code without data word the hi-6110 rt receives a broadcast rt to rt transfer command with 2 data words from the mil-std-1553 bus. the hi-6110 rt is the receiver. the hi-6110 captures the message which is read by the host. a status word is not transmitted. example 10. broadcast rt to rt transfer, hi-6110 is the receiving rt example rt mil-std-1553 message sequences holt integrated circuits 21
hi-6110 (bus monitor mode) figure 3. block diagram - bus monitor (without assigned rt address) mode valmess error rcva rcvb rcvcmda rcvcmdb rflag receiver receiver bus a busa busa message status protocol control busb busb control register status register mt protocol engine bus b manchester decoder serial to parallel manchester decoder serial to parallel host data interface command word 1 command word 2 rx data fifo mt error register message register d15-d0 r/ ra3-ra0 ffempty cs w str bus a word bus b word mode data (r) status word rec'd receiving status word (rt-rt) clk mr bcstart bcmode rtmode bus monitor the hi-6110 may be configured as bus monitor with or without an assigned rt address. resetting both bcmode and rtmode to ?0? configures the hi-6110 as a bus monitor with assigned rt address (mt/rt mode). setting both bcmode and rtmode to ?1? configures the hi-6110 as a bus monitor without an rt address (mt mode). in either mode, the hi-6110 captures all information that occurs on the selected mil-std-1553 bus. all bus transactions are checked for errors. if a message sequence is good, the valmess signal is asserted at the end of the message. if an error occurs, error is asserted. the host may interrogate the error register to determine the nature of the error. command words, status words, message data and mode words are captured for all bus transactions and may be read by the host. in mt/rt mode, the hi-6110 will respond to all mil-std-1553 messages with assigned rt address matching the pin- programmed rt address. all conditions pertinent to rt responses are described in the previous remote terminal mode section of this document. in mt mode (no assigned rt address), the hi-6110 does not transmit information to the mil-std-1553 bus and acts as a passive monitor as described by the mil-std-1553 specification. figure 3 represents the hi-6110 in mt mode. in bus monitor mode, the user must first perform master reset to initialize the mt protocol engine and clear all message registers and data fifos. this may be achieved by pulsing the mr input high, or writing a "1" to control register bit 0. the user must select a master clock (clk) frequency by programming control register bits 11 and 12. refer to the mt register formats section for a full description of available registers and their functions in bus monitor mode. in mt mode (without assigned rt address) the five rt address input pins rta0 to rta4 must be pulled high or left unconnected. in the second case, internal pull-up resistors act to hold the five rta inputs high. in mt mode, the rtap pin is ?don?t care?. initialization holt integrated circuits 22
hi-6110 (bus monitor mode) 1514131211109876543210 msb lsb bus a/b word 15:0 mil-std-1553 message data word 15:0 1514131211109876543210 msb lsb clksel reserved ra3 ra2 ra1 ra0 mrb mra rtmode bcmode not used mr msb lsb 1514131211109876543210 not used ra0 rerr not used not used x x x x0 in mt mode, the bus a word register holds the last valid mil- std-1553 word received on bus a. the bus b word register holds the last valid mil-std-1553 word received on bus b. bus (read only) read address: 1001 bus b word register (read only) read address: 1010 a word register the receive data fifo is 32-words deep and holds all mil- std-1553 received data words. the fifo is cleared at master reset. a low ffempty flag (output pin or status register bit) means fifo data is available to be read by the host. successive data word fetches will cause ffempty to go high when the last data word is read. receive data fifo (read only) read address: 0100 bit name function 10 - 7 ra3:0 register address for hi-6110 register and data read / write operations. the register address is defined by the logical or of these bits and their corresponding input pins. setting control register bits 10:7 to 0000 ensures that just the address input pins control register addressing. 6 rerr reset error. if rerr is low the error output signal is only reset on reception of a new valid setting rerr high resets a high error output . 5 - 4 mrb, mra setting either mra or mrb to "1"connects the to monitor bus a or monitor bus b. the 1553 receiver, manchester decoder and rcv output signal remain operational on the inactive bus. when the monitor terminal receives a command on the inactive bus, its rcv signal output goes high. the mt must switch active buses so received data words, message results, etc. will be stored in the proper registers. v 3 - 2 rtmode, hi-6110 mode select. these control register bits are logically or'ed with their corresponding input pins. the bcmode user can select 1553 operating mode under either hardware or software control: 15-13 - not used in mt mode. 12 clksel selects the frequency of the hi-6110 external clk input, as follows: clksel value 0 24 mhz 1 12 mhz 11 reserved must be reset to ?0? command. (rising edge) if the rerr bit is left high, error outputs will automatically reset after 3 to 4 microseconds. for normal operation, this bit is set to ?1?. protocol engine setting both mra and mrb selects neither bus. alid words received on the inactive bus can be read without changing active bus by reading the bus a word or bus b word register, but any received message words, errors, message results etc. are not updated if the bus is not enabled by setting the appropriate mra or mrb bit. rtmode bcmode 1553 operating mode 0 1 bus controller (bc) 1 0 remote terminal (rt) 1 1 bus monitor without assigned rt address (mt) 0 0 bus monitor with assigned rt address (rt-mt) in which control register bits 5:4 enable transmit for valid commands for which command terminal address matches the assigned remote terminal address. see the rt mode section. 1 - not used in mt mode. 0 mr master reset. writing "1" and then ?0? to this bit performs the same function as pulsing the mr pin. all register and data fifos are cleared when master reset is asserted. the control register is the exception; it is not affected by master reset. the control register value specifies hi-6110 operating mode, clock frequency and specifies which bus is enabled for monitoring. control register bits can also be used for addressing registers in read/write operations, or to assert master reset. control register (r/w) write address: x1xx, read address: 1100 register formats (mt mode) holt integrated circuits 23
hi-6110 (bus monitor mode) 1514131211109876543210 msb lsb rf1 rcvb rcva rf0 rflagn ffempty error valmess idle not used 0000000 message error 1514131211109876543210 msb lsb rt address instrumentation service request reserved rrr broadcast command received busy subsystem flag dynamic bus control acceptance terminal flag message error 1514131211109876543210 msb lsb rt address instrumentation service request reserved rrr broadcast command received busy subsystem flag dynamic bus control acceptance terminal flag bit name function 15- 9 - not used. these bits are set to "0". 8 error this bit is set to "0" after reset or when the last mil-std-1553 message sequence was valid. error is set to a "1" if the last sequence had an error. the nature of the message error can be determined by examining the error register. the error output pin reflects the state of this bit. 7 valmess this bit is a "0" after reset or the last mil-std-1553 message contained an error. valmess goes high on the completion of an error-free mil-std-1553 message sequence. valmess is reset to a zero each time new valid command word is received by the rt. the valmess output pin reflects the state of this bit. 6 rf1 register address bit 1 for the last written word register. 5 rf0 register address bit 0 for the last written word register. 4 rflagn rflagn returns high momentarily upon the receipt of any new 1553 word. the output reflects the state of this bit. 3 ffempty if "0" then the receive data fifo contains at least one word of data. this bit is set to a "1" on reset, or when the user has read all available received data words from the receiver data fifo. the ffempty output pin reflects the state of this bit. 2 rcvb set to a "1" upon receipt of a valid command word. 1 rcva set to a "1" upon receipt of a valid command word. a 0 idle if "1" then the rt is idle. this bit is a zero throughout the time the rt is processing a valid mil-std-1553 command message. the bit returns to a "1" when the message is completed. goes low when a new mil-std-1553 command word is received by the rt, or a status word is received from the receiving rt during an rt - to - rt transfer. the rcvb output pin mirrors the state of this bit. the rcv output pin mirrors the state of this bit. rflag the status register may be interrogated by the host at any time. it provides information that allows the user to determine whether the hi-6110 mt is busy monitoring an active mil- std-1553 message and its progress. after a message sequence has completed, the status register indicates whether an error was detected or if the message sequence was successful. status register (read only) read address: 0101 used only for rt to rt messages, the status word 2 register holds the mil-std-1553 status word sent by the receiving remote terminal. status word register (read only) read 2 address: 0011 for non-broadcast single-rt commands, the status word 1 register holds the mil-std-1553 status word transmitted by the rt. for rt to rt messages, the status word 1 register holds the mil-std-1553 status word sent by the transmitting remote terminal. status word register (read only) read 1 address: 1000 mt operation holt integrated circuits 24
hi-6110 (bus monitor mode) msb lsb 1514131211109876543210 0 0 13 12 not used 11 10 98765432 0 1 message type flags manerr norcv 1514131211109876543210 msb lsb 00000 fferr not used ocnerr gaperr cwerr syncerr not used rtparerr 0 0 not used 0 15:11 10 9:5 4:0 15:11 10 9:5 4:0 rta 0 xxxxx 11111 0 00001 - 11110 00001 - 11110 xxxxx rta 0 00001 - 11110 xxxxx xxxxx 1 00001-11110 xxxxx 11111 0 00001 - 11110 xxxxx not rta 1 00001-11110 xxxxx rta 1 00001 - 11110 xxxxx rta 1 0000 or 11111 0xxxx command word 2 11111 1 0000 or 11111 0xxxx only applies for rta 0 0000 or 11111 0xxxx rt-rt commands 11111 0 0000 or 11111 0xxxx rta 1 0000 or 11111 1xxxx 11111 1 0000 or 11111 1xxxx rta 0 0000 or 11111 1xxxx 11111 0 0000 or 11111 1xxxx non-mode commands 0001 receive command from bc, not broadcast 0080 0004 rt-rt command, 0100 0402 transmit command, rt 0410 o m 0400 * receive command from bc, broadcast not broadcast rt-rt command, broadcast to bc mc0 - mc15 t/r=1 n ode data, not broadcast mc0 - mc15 t/r=1 no mode data, broadcast 0410 mc0 - mc15 t/r=0 not broadcast, undefined 0400 mc0 - mc15 t/r=0 broadcast , undefined 2420 mc16 - mc31 t/r=1 mode data, not broadcast 0400 * mc16 - mc31 t/r=1 broadcast , undefined 0040 mc16 - mc31 t/r=0 mode data, not broadcast 0800 mc16 - mc31 t/r=0 mode data, broadcast * two cases where 0400 is reset 550ns after rcv mode code commands command word 1 bit fields command word 2 bit fields hex last valid command decoded the message register identifies command type when a new valid command is received from the mil-std-1553 bus controller. when a valid command is received, message type is decoded and appropriate message register bit(s) are set. register bits 5 and 13 are mirrored. broadcast commands occur when command word bits 15:11 = 11111. v alues other than 11111 indicate the remote terminal address for a non-broadcast command. message register bit 10 is set for any mode code or transmit command. this enables detection of the three undefined mode code command types listed under bit 10 below. message register (read only) read address: 0110 bit name function 15- 10 - not used. these bits are set to "0". 9 rtparerr rt parity error: there is a parity error in the pin-programmed rt address of this rt. 8- 7 fferr data was not available in the transmit data fifo. 6 - not used. 5 conerr contiguous message error: transmission was not contiguous. 4 gaperr bus activity was detected in the 4.0 us gap after a valid message was completed. 3 wcerr word count error. 2 syncerr sync error: expected command sync and got data sync, or vice versa. 1 manerr manchester encoding error: the decoder detected an error in manchester encoding, bit count or parity. 0 norcv not used. this bit is set to "0". this bit is set to "0". this bit is set when a data word is expected while processing a receive command, but a gap is detected. it is also set when an rt-to-rt "no response timeout" occurs, as defined per mil-hdbk-1553, figure 8 "rt-rt timeout measurement". the hi-6110 asserts this error when the bus dead-time between the rt- rt command pair and the transmit rt status word exceeds 15 us. the rt error register is cleared at reset and on receipt of a valid mil-std-1553 command word. if an error is encountered during message execution, the error pin goes high, the error bit is set in the status register, and one or more bits are set in the error register. the host may interrogate the error register at any time to determine the type of error encountered. error register (read only) read address: 0111 mt operation holt integrated circuits 25
hi-6110 (bus monitor mode) mode data word 15:0 1514131211109876543210 msb lsb t/r 1514131211109876543210 msb lsb rt address subaddress / mode data word count / mode code t/r 1514131211109876543210 msb lsb rt address subaddress / mode data word count / mode code the read-only receive mode data register holds the mode code data word received during a mode code with data word (receive) command. receive mode data register (read only) read address: 0010 t from the last rt-rt message. whenever rcv is asserted, rt-rt messages can be detected by checking message register bits 2 and 8. he command word 2 register contains the second (transmit) command word (see note above for command word 1.) command word 2 register (read only) read address: 0001 for all commands except rt to rt, the command word 1 register contains the last valid command word received. when rcv is asserted, if message register bit 2 or bit 8 is set, the new message is rt to rt. the command word 1 register holds the first (receive) command and the command word 2 register holds the second (transmit) command. command word 1 register (read only) read address: 0000 mt operation bus monitor operation (mt mode) when configured as a bus monitor with no assigned rt address, the hi-6110 continuously monitors the selected mil-std-1553 bus and passively captures all bus traffic. the hi-6110 never transmits information onto the bus. when a command word is received, a validation check is performed. if the command word contains no errors, the pin goes low and the hi-6110 mt captures the complete message in its internal registers and receiver data fifo as appropriate. if the valid command word was received on bus a, the rcva signal goes high to notify the host that a new message has commenced. the rcvb pin is asserted when the valid command word arrived on bus b. the command word may be read from the command word 1 register, or the message register can be read to directly learn the type of command received. if the monitored mil-std-1553 system utilizes rt-rt commands, special precautions arise if superseding commands may occur on the same bus. consider this unusual sequence of events: a) an rt-rt command pair is received. command word 1 addresses the receiving rt (called "rxrt" in this example) and command word 2 addresses the transmitting rt (called "txrt"). b) following the rt-rt command pair, the bus monitor normally expects to see the txrt status word followed by the commanded number of data words. instead, the word following the rt-rt command pair has command sync and is addressed to the rxrt (not the txrt). the hi-6110 bus monitor treats the unexpected word as a superseding command for the rxrt. monitor processing stops for the rt-rt message stops. the new command word is stored in the command word 1 register and the hi-6110 stores message results for the new superseding message in the appropriate registers. to assure this treatment for the rxrt superseding command, the host should apply master reset after completion of any fulfilled rt-rt command, following all necessary register operations by the host. this reset should be performed before reception of the next rt-rt command that might be followed by a superseding command to the rxrt occuring before the txrt response. the above paragraph describes an unlikely occurrence because the bc's transmission of a superseding command is likely to collide on the bus with the txrt response to the original rt-rt command. rflag holt integrated circuits 26
hi-6110 (bus monitor mode) bus monitor operation (mt/rt mode) when configured as a monitor with assigned rt address, the hi- 6110 responds to all commands that match its hard-wired rt address as described in the rt section of this data sheet. all other bus traffic is monitored as described in this mt section. to operate as monitor with assigned rt address, control register bits 3:2 are reset to 00. in this operating mode, the monitor asserts rcv for rcva or rcvb upon detection of any properly encoded command occurring on bus a or bus b. assertion of rcv indicates either a monitored command, or a valid command which requires a monitor terminal response. if received command word bits 15:11 match the assigned terminal address present on input pins rta4:0 and parity bit rtap, the device will respond to the command as the addressed terminal. when rcv is asserted, there is no way to distinguish valid commands from monitored commands, using only the hi-6110 output signals available to the host. valid commands (that is, commands with address match) can occur in command word 1 or command word 2. detection of valid commands has higher priority than detection of monitored commands because many valid commands require timely host servicing of hi-6110 registers for fulfillment. here is a logic sequence to distinguish valid commands from monitored commands: when rcva or rcvb is asserted, the host reads the message register. register values 0x1008 and 0x0200 only occur for rt-rt transmit commands in remote terminal mode. these values never occur for monitored commands. if the message register contains either value, the decoded command is a valid rt-rt transmit command, and the command word 2 register contains the transmit command to which the monitor terminal must respond. detection of valid command requires immediate host action to fulfill message requirements; the host must load the hi-6110 transmit fifo in time for data transmission. steps 2-4 are skipped. when command word 2 does not contain 0x1008 or 0x0200, newly decoded command word 1 must be tested for address match to the monitor's assigned terminal address to detect command validity. the host must read the command word 1 register, looking for a value match between the word's upper 5 bits and the 5-bit value present at hi-6110 rta4:0 input pins. a signal path must be provided so the host can directly read the 5-bit rta4:0 value, as the terminals' active address value cannot be determined by reading hi-6110 registers. when command word 1 address match occurs, the host must take all necessary steps to fulfill the valid command. for example, when transmit commands occur, the host must load the hi-6110 transmit fifo in time for data transmission, following the same rules presented for dedicated remote terminal operating mode. broadcast commands in command word 1 register are considered valid to the monitor's assigned terminal address. unless the monitor's assigned terminal address must recognize and act upon broadcast messages, there is no need to test for cw1 broadcast 11111 terminal address match since no response is transmitted for broadcast commands. if step 2 test fails but broadcast commands are allowed, test cw1 address match to 11111 to detect (or rule out) valid broadcast messages. ruling out a valid command in steps 1-3 means the new command in cw1 is monitored. if the message register value is either 0x0004 or 0x0100, the message is a monitored rt-rt sequence and cw2 is also involved in the message. control register bits 4-5 designate the active and inactive buses. when the hi-6110 is idle, one of these bits is usually set, reflecting the bus where the last command was serviced. the bus corresponding to the set control register bit is designated ??active? while the bus corresponding to the reset bit is designated ?inactive?. when a new command is decoded, a rcva or rcvb output is asserted. when rcv occurs on the inactive bus, the host should toggle hi-6110 control register bits 4-5 to switch active / inactive buses and service the new command. under unusual conditions, a new command can occur on the inactive bus while the device is still processing an earlier command on the active bus. monitoring of the first message (or response, if the command matched the monitor terminal assigned rt address) is unaffected by rcv assertion for the overlapping command on the inactive bus. however processing will stop for an unfinished message on the active bus whenever the host toggles hi-6110 control register bits 4-5 to switch active / inactive buses to service the new command. this is consistent with mil-std-1553, which says a new command has priority over an earlier command. building on the above scenario, the host switches active bus whenever rcv assertion indicates a new command was detected on the inactive bus. when the monitor is operating with assigned rt address, each rcv assertion can indicate a monitored command, or a valid command matching the monitor terminal assigned rt address. when command address match occurs for a new ?inactive bus? command, switching active bus by writing control register bits 5-4 disrupts the terminal's ability to transmit a command response. the hi-6110 does not respond to the command that caused bus switching to occur. once bus switching occurs, all following commands on the same bus (monitored or with matching address) are fully processed by the terminal. monitored commands without rt address match (or all commands when operating in monitor mode without assigned rt address) are correctly handled by the hi-6110, even when they occur on the inactive bus and the host switches buses to service/monitor the message. 1. detect (or rule out) a valid rt-rt transmit command in the cw2 register 2. detect (or rule out) another valid command in the cw1 register 3. detect (or rule out) a valid broadcast message in the cw1 register 4. process the monitored message monitor terminal with or without assigned rt address monitor terminal with assigned rt address only holt integrated circuits 27
hi-6110 (bus monitor mode) receive command data word 1 data word 2 status word 1 from bus controller from transmitting rt mil-std-1553 bus str host read cw1 (receive command) host read swr (status word 1) host read cw2 (transmit command) transmit command status word 2 from receiving rt ffempty host read data fifo (data word 2) host read data fifo (data word 2) host read receiving status word (sw2) valmess rcva/b rcmda/b transmit command data word 1 data word 2 status word from bus controller from responding rt mil-std-1553 bus str host read status word received host read cw1 (command word) rcva/b valmess ffempty host read data fifo (data word 1) host read data fifo (data word 2) receive command data word 1 data word 2 data word 3 status word from bus controller from responding rt mil-std-1553 bus str host read data fifo (data word 1) host read data fifo (data word 2) host read cw1 (command word) host read data fifo (data word 3) host read status word received valmess rcva/b ffempty rcmda/b the hi-6110 mt monitors an rt to rt transfer with 2 data words command on the mil-std-1553 bus. the hi-6110 captures the message data and the status words from both the transmitting and receiving rts. example 3. rt to rt transfer the hi-6110 mt monitors a transmit command with 2 data words on the mil-std-1553 bus. the hi-6110 mt captures the command word from the bc and the status word and message data from the responding rt. example 2. rt to bc transfer the hi-6110 mt monitors a receive command with 3 data words fon the mil-std-1553 bus. the hi-6110 captures the message data words and does not respond to the bus. example 1. bc to rt transfer example mt mil-std-1553 message sequences holt integrated circuits 28
hi-6110 (bus monitor mode) mode code command mode data status word from bus controller from responding rt mil-std-1553 bus str host read message register host read mode (mode data) valmess ffempty host read status word received rcva/b mode code command mode data status word from bus controller from responding rt mil-std-1553 bus str host read status word received host read cw1 (control word) valmess ffempty host read mode (mode data) rcva/b mode code command status word from bus controller from responding rt mil-std-1553 bus valmess str host read cw1 (command word) ffempty host read status word recived rcva/b the hi-6110 mt monitors a mode command with data word (receive) on the mil-std-1553 bus. the mode data word from the bc and the status word from the responding rt are captured by the hi-6110 mt and read by the host. example 6. mode code with data word (receive) the hi-6110 mt monitors a mode command with data word (transmit) on the mil-std-1553 bus. the status word and mode data word from the responding rt are captured and read by the host. example 5. mode code with data word (transmit) the hi-6110 mt monitors a mode code command on the mil- std-1553 bus. the responding rt's correct status word is captured. example 4. mode code command without data word example mt mil-std-1553 message sequences holt integrated circuits 29
hi-6110 (bus monitor mode) mode code command from bus controller mil-std-1553 bus valmess str host reade cw1 (command word) ffempty rcva/b receive command data word 1 data word 2 status word 1 from bus controller from transmitting rt mil-std-1553 bus str host read cw1 (receive command) host read data fifo (data word 1) transmit command ffempty host read cw2 (transmit command) host read status word received host read data fifo (data word 2) valmess rcva/b rcmda/b receive command data word 1 data word 2 data word 3 from bus controller mil-std-1553 bus str host read cw1 (command word) host read data fifo (data word 1) host read data fifo (data word 2) host read data fifo (data word 3) ffempty valmess rcva/b rcmda/b the hi-6110 mt monitors a broadcast mode command without data word on the mil-std-1553 bus. the mode command word is read by the host example 9. broadcast mode code without data word the hi-6110 mt monitors a broadcast rt to rt transfer command with 2 data words on the mil-std-1553 bus. the hi- 6110 mt captures the message data and the status word from the transmitting rt. note the behavior of the ffempty signal when the first data word is read, temporarily emptying the fifo, before message completion. example 8. broadcast rt to rt transfer the hi-6110 mt monitors a broadcast receive command with 3 data words on the mil-std-1553 bus. the message data is captured and read by the host example 7. broadcast bc to rt transfer example mt mil-std-1553 message sequences holt integrated circuits 30
hi-6110 (bus monitor mode) reg addr t ars valid t arh t csrh t drh t drs t csrs figure 5. data bus cs str r/w t rwrh t rwrs t str valid refer to ac electrical characteristics table mode code command from hi-6110 bc mil-std-1553 bus valmess str host read cw1 (command word) host read mode (mode data) mode data ffempty rcva/b valid figure 4. t aws t awh t cswh t dwh t dws t csws t rwwh t rwws reg addr valid data bus cs str r/w t str refer to ac electrical characteristics table data bus timing - read data bus timing - write data bus timing diagrams the hi-6110 rt receives a broadcast mode command with data word from the mil-std-1553 bus. the host reads the mode data word received. example 11. broadcast mode code with data word example mt mil-std-1553 message sequences holt integrated circuits 31
hi-6110 parameter symbol condition min typ max units operating voltage vdd 3.15 3.30 3.45 v power supply current icc1 not transmitting 4 10 ma see note 1 below icc2 continuous supply current while 750 800 ma one bus transmits @ 100% duty cycle, 70 ohm resistive load device power dissipation pd1 not transmitting 60 mw pd2 transmit one bus @ 100% duty 650 750 mw cycle, 70 ohm resistive load min. input voltage (hi) v digital inputs 70% v max. input voltage (lo) v digital inputs 30% v min. input current (hi) i digital inputs 20 a max. input current (lo) i digital inputs -20 pull-up / pull-down current digital inputs and data bus 275 min. output voltage (hi) v i = -1.0ma, digital outputs 90% v max. output voltage (lo) v i = 1.0ma, digital outputs 10% v input resistance r differential 20 kohm input capacitance c differential 5 pf common mode rejection ratio cmrr 40 db input level v differential 9 vp-p input common mode voltage v -5.0 5.0 v-pk threshold voltage - direct-coupled detect 1.15 20.0 no detect 0.28 theshold voltage - detect 0.86 14.0 no detect 0.20 see note 2 below a i a v 1 mhz sine wave vp-p v (measured at point ?a ? in figure 6) vp-p transformer-coupled v 1 mhz sine wave vp-p v (measured at point ?a ? in figure 7) vp-p = ih il ih il oh out ih out d dd dd dd dd pud receiver (measured at point ?a ? in figure 6 unless otherwise specified) in in in icm thd thnd thd thnd d t vdd = 3.3 v, gnd = 0v, t = operating temperature range (unless otherwise specified). a dc electrical characteristics note: stresses above absolute maximum ratings or outside recommended operating conditions may cause permanent damage to the device. these are stress ratings only. operation at the limits is not recommended. supply voltage temperature range industrial ........................ -40c to +85c extended ..................... -55c to +125c vdd .................................... 3.3v... 5% supply voltage ( logic input voltage range power dissipation at 25c 1.0 w solder temperature 275c for 10 sec. junction temperature 175c storage temperature -65c to +150c vdd) -0.3 v to +5 v -0.3 v dc to +3.6 v receiver differential voltage 10 vp-p driver peak output current +1.0 a recommended operating conditions absolute maximum ratings note 1: in actual use, the highest practical transmit duty cycle is 96%, occurring when a remote terminal responds to a series of 32 data word transmit commands (rt to bc) repeating with minimum intermessage gap of 4us (2us dead time) and typical hi-6110 rt response delay of 5us. note 2: w he power delivered by the 3.3vdc power supply is 3.3v x 750ma typical = 2.48w. most of the transmit power (2.48w - 0.65w = 1.83w) is dissipated in the bus load, not in the device. hile one bus continuously transmits, t holt integrated circuits 32
hi-6110 parameter symbol min typ max units t t t t t t t t t strobe pulse width 50 -- -- ns address write setup time 0----ns address write hold time 100 -- -- ns data 30 -- -- ns 30 -- -- ns 50 -- -- ns write hold time 30 -- -- ns r/ write setup time 0----ns r/ write hold time 30 -- -- ns data bus timing - write (see figure 4) data bus timing - read (see figure 5) str cs cs w w str aws d dwh csws , only writes to reg. address x010, reset transmit fifo address write hold time, all other register write operations 30 -- -- ns write setup time data write hold time write setup time strobe pulse width 90 -- -- ns address read setup time 0----ns address read hold time 30 -- -- ns data read setup time -- -- 150 ns data read hold time -- 60 -- ns read setup time 0----ns read hold time 30 -- -- ns r/ read setup time 20 -- -- ns r/ read hold time 30 -- -- ns awh ws cswh rwws rwwh t t t t t t t t t t awh arh s csrh rwrs rwrh str cs cs w w str ars d drh csrs r parameter symbol test conditions min typ max units rise time tr 35 ohm load 100 -- 300 ns fall time tf 35 ohm load 100 -- 300 ns inhibit delay tdi-h inhibited output -- 100 ns tdi-l active output -- 150 ns transmitter (measured at point ?a ? in figure 6) d vdd = 3.3 v, gnd = 0v, t = operating temperature range (unless otherwise specified) a ac electrical characteristics parameter symbol condition min typ max units output voltage direct coupled 35 ohm load 6.0 9.0 vp-p 70 18.0 27.0 vp-p output noise v differential, inhibited 10.0 mvp-p output dynamic offset voltage v -90 90 mv -250 250 mv output resistance r differential, not transmitting 10 kohm output capacitance c 1 mhz sine wave 15 pf transmitter (measured at point ?a ? in figure 6 unless otherwise specified) d v transformer coupled v ohm load (measured at point ?a ? in figure 7) direct coupled 35 ohm load transformer coupled v 70 ohm load (measured at point ?a ? in figure 7) out out dyn t t on dyn out out vdd = 3.3 v, gnd = 0v, t = operating temperature range (unless otherwise specified) a dc electrical characteristics (cont.) holt integrated circuits 33
hi-6110 rx data to manchester decoder txinha/b transmitter busa/b busa/b 52.5 (.75 zo) 52.5 (.75 zo) 2.5:1 1:2.5 1:1.4 1.4:1 35 (.5 zo) coupling transformer coupling transformer isolation transformer isolation transformer receiver 52.5 (.75 zo) 52.5 (.75 zo) 35 (.5 zo) tx data from manchester encoder point ?a ? t point ?a ? t isolation transformer point ?a ? d txinha/b transmitter receiver 1:2.5 55 55 35 2.5:1 55 55 35 busa/b busa/b rx data to manchester decoder tx data from manchester encoder isolation transformer point ?a ? d heat sinking the leadless plastic chip carrier package the hi-6110pci/t/m is packaged in a 64-pin plastic chip- scale package (qfn). this package has a metal heat sink pad on its bottom surface which should be soldered to a metalized pad on the printed circuit board. is electrically isolated from the die. the heat sink may be connected to vdd, gnd or left floating. for optimum thermal dissipation the heat sink applications note holt applications note an-500 provides circuit design notes regarding the use of holt mil-std-1553 data communications devices. layout considerations, as well as recommended interface and protection components are included. figure 7. transformer coupled test circuits figure 6. direct coupled test circuits redundant "vias" between the exposed board surface and an internal vdd or gnd power plane will enhance thermal conductivity. holt integrated circuits 34
hi-6110 64 - 61 rta4 60 rta3 59 rta2 58 rta1 57 rta0 56 rtmode 55 bcmode 54 rcv a 53 txinha 52 - 51 - 50 - 49 - 63 vddlog- 62 rtap 48 - 46 vdda 4 44 busb 43 vddb 4 41 txinhb 40 rcvb 39 ffempty 38 rf0 / rcvcmda 37 rf1 / rcvcmdb 3 35 valmess 34 error 33 mr 47 busa 5 busa 2 busb 6 rflag d10 17 d11 18 d12 19 d13 20 d14 21 d15 22 ra2 23 ra1 24 ra0 25 bcstart 26 ra3 27 clk 28 gnd 29 -30 -31 -32 -1 2 r/ 3 4 -5 d0 6 d1 7 d2 8 d3 9 d4 10 d5 11 d6 12 d7 13 d8 14 d9 15 str w cs -16 hc-6110pci hc-6110pct 64 pin leadless plastic chip carrier (qfn) see page 1 for 52-pin pqfp pin configuration pin configuration (top view) part number package style condition junction temperature hi-6110pci / t 52 pin pqfp 64 pin qfn heat sink pad unsoldered mounted on circuit board heat sink pad soldered hi-6110pqi / t 60.9 c/w 22.8 c/w 31.1 c/w 56c t = 25c a ja t = 85c a t = 125c a 41c 37c 116c 101c 97c 156c 141c 137c data taken at vdd = 3.3v, continuous data transmission at 1 mbit/s, single transmitter enabled. thermal characteristics holt integrated circuits 35
hi-6110 part package number description pc 64 pin plasti c 9 x 9mm chip scale qfn (64pcs) not available with ?m? flow pq 52 pin plastic quad flat pack pqfp (52ptqs) part temperature burn number range flow in i -40c to +85c i no t -55c to +125c t no m -55c to +125c m yes part package number description blank tin / lead (sn / pb) solder f 100% matte tin (pb-free rohs compliant) hi-6110 xx x x ordering information holt integrated circuits 36
hi-6110 revision history dwg. no. rev. date description of change ?status word 2 register? m 08/12/08 expanded section entitled ?bus monitor operation (mt/rt mode).? this includes all text in the section?s second, added page. renumbered all following pages. ds6110 l 05/01/08 in bc mode, error register bit 4 changed to ?not used?. in rt mode, revised text for ?transmit data fifo,? ?reset transmit data fifo?. in mt mode, revised text for ?status word 1 register,? in mt mode, expanded text describing ?bus monitor operation (mt mode)? table ?data bus timing - write? added new line for address write hold time n 12/15/08 revised ac electrical characteristics modified qfn and pqfp package dimensions to be consistent with current package vendor. o 02/06/09 clarified description of internal pull-up & pull-down resistors. clarified temperature ranges. p 03/19/09 clarified initialization state of the transmit status word register for remote terminal mode. q 03/10/10 clarified in pin description table. power supply currents and power dissipation revised for worst case load. r 05/03/10 corrected the electrical characteristic description of the heat sink pad on the bottom of the qfn package. rflag holt integrated circuits 37
hi-6110 package dimensions bsc = ?basic spacing between centers? is theoretical true position dimension and has no tolerance. (jedec standard 95) d etail a see detail a 0 7 .520 (13.2) bsc sq .394 (10.0) bsc sq .063 (1.6) typ .063 (1.6) .055 .002 (1.40 .05) .008 (.20) min .005 (.13) r min r min .005 (.13) .0256 (.65) bsc .0145 .0035 (.375 .075) .035 .006 (.88 .15) package type: 52ptqs inches (millimeters) 52-pin plastic quad flat pack (pqfp) bsc = ?basic spacing between centers? is theoretical true position dimension and has no tolerance. (jedec standard 95) package type: 64pcs inches (millimeters) 64-pin plastic chip-scale package (qfn) heat sink pad on bottom of package. heat sink may be left floating or connected to vdd or gnd. .354 (9.00) bsc .039 (1.00) max .008 (0.20) typ .0197 (0.50) bsc .010 (0.25) typ .016 .004 (0.40 ) .10 .281 .003 (7.125 ) .075 .281 .003 (7.125 ) .075 bottom view top view .354 (9.00) bsc max. holt integrated circuits 38

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